Using Makefiles

The basic aims of makefiles and make facilities are to:

• automate the building and/or installation of software from source
• simplify and expedite the frequent update of libraries and executables during software development.

Indeed, the make tool is probably the most widely used tool for these purposes in the UNIX community.

The essential components of a makefile are the target building rules. These consist of a line naming a target (usually a filename) and its dependencies (generally the files that the target depends on) followed by lines (starting with a TAB character) giving the actions (as shell commands) needed to construct the target from the dependencies, e.g.

target : dependency1 dependency2
[TAB]     rm -f target
[TAB]     cat dependency1 dependency2 > target

Basically the make command checks the last modified date on all the dependencies to see if any have been updated more recently than the target - if so then the build actions are applied. In terms of software builds and installs, there is likely to be a hierarchy of build rules - how to construct objects and libraries from source, how to construct executables from objects and libraries and how to install executables. make recursively checks all these dependencies and updates in the correct order (bottom up) so that all targets are up-to-date compared with all their dependencies.

Most make facilities also provide a sophisticated set of macro constructs to generate and generalize complicated dependencies and build actions. The simplest macro definition looks like:

F77_FLAGS = -g -extend -r8

Any instances of ${F77_FLAGS} or $(F77_FLAGS) in build rules or subsequent macro definitions will be replaced by the string -g -extend -r8 .

Within build rule actions, there are special macros dynamic set to the current target and dependencies. For example $@ is the current target, $< is the dependent and $(@F) is the filename part of the current target (without the path). Suffix rules can be used to associate targets and dependents through common filename bases. For example, .c.o indicates that the object file depends on the correspondingly named .c file.

Example

The following is a simple makefile illustrating macros and suffix rules. The source files sub1.f90, sub2.f90, fn1.f90, fn2.f90 and main.f90 must exist. In this case, the command

make graf

will bring the executable graf up-to-date.

OBJECTS = sub1.o  sub2.o fn1.o  fn2.o main.o
LIBS = -lX11 -limsl
F90_FLAGS = -extend -r8

graf : $(OBJECTS)
	f90 $(OBJECTS) $(LIBS) -o graf

.f90.o :
	f90 -c $(F90_FLAGS) $<